1. Field of the Invention
This invention is related to the field of processors and embedded controllers and, more particularly, to interrupt mechanisms within processors and embedded controllers.
2. Description of the Related Art
Processors are generally used to execute instruction sequences designed to perform a desired operation in a computer system. The instruction sequence as well as associated processor and system state is referred to herein as a "task". General purpose processors are frequently used as the central processing unit of general purpose computer systems. Additionally, processors are integrated with various types of peripheral logic to form embedded controllers. These controllers may be used to perform computing functions in non-general purpose computer environments (e.g. disk drive controllers, cellular phones, personal digital assistants, electronic control systems used in non-electronic environments such as automobiles, etc.).
Processors are further used, in addition to executing tasks, to provide interrupt services to other devices coupled to the processor (either integrated into embedded controller with the processor, or coupled to the processor in either a general purpose environment or an embedded controller environment). Generally, the interrupt services are requested when the hardware employed within these other devices determines that a situation exists which the hardware itself is not configured to handle. For example, a device may include a buffer for storing data which is to be transferred to another device within the computer system (e.g. a memory). If the buffer becomes full, the device may need service from the processor to empty the buffer. By using the processing power within the processor, the hardware employed within these devices may be simplified (since the hardware need not handle the situation) and separate processors need not be included within the devices to provide the instruction execution resources needed to provide the service.
Typically, devices inform processors of the need for service by asserting an interrupt signal to the processor. In response to the interrupt signal, the processor suspends execution of the current task to execute an interrupt service routine. The instructions within the interrupt service routine cause the processor to communicate with the device needing the service (the "interrupt source"). By executing the interrupt service routine, the processor determines the service needed by the device and performs the service. Subsequently, the processor resumes execution of the interrupted task.
Unfortunately, implementing interrupts in a processor is a complicated matter. Because the purpose of the interrupt may have nothing to do with the interrupted task, the interrupt service routine generally executes transparently to the interrupted task. Several features of performing an interrupt help to ensure the transparency of the interrupt. First, the task is suspended at a particular point within the instruction sequence. Each instruction prior to the particular point has completed execution, and none of the instructions subsequent to the particular point have executed. Second, the "context" (e.g. processor state including register values used by the task) is stored for restoration after the interrupt service routine is executed (e.g. typically stored in a context save area reserved by the operating system within memory). Responsibility for correctly saving and restoring the context may be assigned to hardware (e.g. processor hardware invoked when the interrupt is signalled) or software (e.g. the interrupt service routine).
Both of the aforementioned interrupt features may be complicated to implement and/or may impact performance of the processor. Suspension of the currently executing task is complicated by the fact that the interrupt may be signaled at any arbitrary point during execution of the task. Modem processors are often configured with complex instruction processing pipelines and/or multiple instruction processing pipelines. Correctly suspending the instruction sequence (such that a point can be defined within the instruction sequence for which each instruction prior to that point has completed execution and each instruction subsequent to that point has not executed) may be highly complicated. Furthermore, verifying that arbitrary interrupt may occur and that the executing task may be correctly suspended is difficult.
While successfully saving and restoring the state of the processor may be less complicated to implement than correctly suspending the task, saving and restoring state may be a time-consuming activity which may impact overall execution performance. Accordingly, a method for providing services typically requested by signalling interrupts to the processor is desired.